In the design of a complex integrated circuit (IC), one of the first steps is the preparation of a mathematical model of the proposed circuit. The mathematical model is used to simulate the operation of the proposed circuit and thereby confirm that an IC that performs in the manner of the model will, in fact, accomplish the desired result. Assuming that the simulation shows that the IC will perform as desired, the mathematical model is used to generate the fabrication masks for the IC. Once the masks have been generated, a prototype IC can be manufactured.
The manufacture of a complex integrated circuit, such as a microprocessor, a computer interface, a complex combinational logic circuit, etc., is an extremely costly and time-consuming operation. For this reason, it is important that errors in design of the IC be identified as soon as possible, before commencing manufacture of production parts. Therefore, it is usual to test a prototype IC, by comparing the operation of the prototype IC with the operation of the mathematical model, so that if the comparison indicates a design defect, the design of the IC can be altered before resources are committed to manufacture of production ICs.
Clearly, since the fabrication masks are generated directly from the mathematical model, the prototype IC should perform precisely in accordance with the mathematical model provided that the operation of generating the fabrication masks is performed properly and there are no manufacturing defects. However, the design system used for generating the masks might result in masks being produced that, for example, do not provide sufficient tolerance on the spaces between certain elements of the IC. The IC with no manufacturing defects might then function satisfactorily under ideal conditions of temperature, supply voltage, clock frequency, etc., but not perform adequately under more stringent conditions. As the operating conditions are made increasingly severe, successively more subtle design defects may manifest themselves.
It will be understood by those skilled in the art that exhaustive testing of a complex IC is itself a time consuming operation. When using a conventional semiconductor test system, such as the Tektronix S-3295, the mathematical model is used to make a software simulator of the desired IC, and input vectors, generated with the aid of the mathematical model, are applied to the simulator, as if it were the actual IC performing under normal conditions, and the output vectors generated by the IC are stored. The two sequences of vectors form a data base that is used to test the prototype IC. The test system then applies the same sequence of input vectors to the input port of the circuit and examines the output port, and by comparing each actual output vector with the output vector that was previously obtained using the simulator, the test system can determine whether the prototype circuit has provided the correct response to the input vector and thus whether the prototype circuit contains a design defect.
It will be appreciated that this type of test does not yield very detailed information concerning the location of the defective circuit element. In order to mitigate this disadvantage, some complex integrated circuits are designed with two distinct operational modes, namely a normal mode, in which the circuit performs its normal function in relation to other circuits, and a diagnostic mode which is specifically intended to facilitate testing of the circuit. One feature that may be designed into such a circuit is a serial scan capability. Thus, as shown in FIG. 1, a computer interface circuit 2 may receive an input vector at its input port 4 on 100 or so lines, and the circuit performs various logical operations upon the digits of the input vector in order to provide an output vector at the output port 6. Assuming that these logical operations can be broken down into several discrete stages, the input vector is applied, by way of the input port, to a first logic stage 10 which performs a first series of logical operations and provides at its output a first intermediate vector on lines 12. The intermediate vector may contain 100 or so bits and accordingly the output from the first logic stage would itself have 100 or so lines. The output lines of the first logic stage 10 are connected to the inputs of respective cells of a shift register 14. Depending on the condition of a status pin 15, the shift register is operable either as a parallel-in, parallel-out register (normal mode) or as a parallel (or serial) -in, serial-out register (diagnostic mode). In the normal mode, the first intermediate vector that is clocked into the shift register 14 is immediately clocked into a second logic stage 16. The second logic stage performs logical operations on the first intermediate vector and provides at its output port 18 a second intermediate vector on lines 22. Again, the second intermediate vector might comprise 100 or so bits. The second intermediate vector is clocked into a second shift register 20. In addition to providing the second intermediate vector, the second logic stage might provide a subsidiary vector to the first logic stage on lines 24.
In the normal mode, the vector that is clocked into the shift register 20 is immediately clocked into a third logic stage, which provides at its output port the ultimate output vector of the circuit. The third logic stage might also provide one or more subsidiary vectors on lines 26 to the first and second logic stages for use in the logical operations performed by those stages.
The shift registers 14 and 20 are included in the circuit in order to provide an indication of the status of the internal components of the circuit. Thus, if the voltage level applied to the status pin 15 places the shift registers in their diagnostic mode the intermediate vectors are made available to the exterior of the circuit by way of a serial scan port 28. This could be done by connecting the several shift registers in series, with the final cell connected to a single serial scan output pin, so that the intermediate vectors are clocked through the registers in series and the bits of the vectors can be examined sequentially. It will also be recognized that, with appropriate connections to the internal shift registers of the IC for example a scan input pin 29, particular vectors may be clocked into the IC to initialize the registers to a preferred state. This may result in saving test time, since a very long sequence of input vectors may be required to place the registers in the same state. Thus, both the ability to initialize the registers and to read out the intermediate vectors result from use of the scan testing technique.
Although the intermediate vectors may be clocked out of the IC through a single serial scan output pin, a more favorable arrangement is one in which each register is connected to its own serial scan pin of the port 28, as shown in solid lines in FIG. 1. Because each shift register may comprise 100 or more cells, even when each shift register has its own serial scan pin the operation of clocking the intermediate vectors out of the shift registers is quite time consuming. It is therefore preferred that each shift register be broken down into several segments, so that there is a total of, e.g., 16 segments, and each segment is connected to its own pin of the serial scan port as shown in broken lines in FIG. 1. Obviously, it is desirable that each segment contain substantially the same number of cells.
In the art of design and manufacture of large integrated circuits, the term "vector" denotes a digital word. Thus, an input vector is a digital word that is applied to the input port of the IC. Generally, the individual digits of a vector exist in parallel on respective lines of a multiple line conductor, and it is in this sense that the term "intermediate vector" is applied to the digits that enter the shift register 14 on the lines 12. However, when these digits are clocked out of the shift register in the diagnostic mode of the IC, they are clocked out in series, not in parallel. Nevertheless, because of the origin of the digits it is convenient to continue to refer to them as a vector, specifically as a serial scan vector. Hereinafter, the term "serial scan vector" is used to refer to a vector, or a part of a vector, that is generated in the interior of an IC and the digits of which are made available sequentially at the exterior of the IC.
As before, in order to test a circuit of the kind shown in FIG. 1, a software simulator of the circuit is made from the mathematical model, and one or more input vectors 30 (FIG. 2), simulating the operating conditions of the IC, are applied to the input port of the simulator with the shift registers 14, 20 in the normal mode. The registers are then switched to the diagnostic mode and the serial scan vectors 32 are clocked out of the output port of the simulator. In addition, the next intermediate vector may be scanned into the shift registers from the scan input pin 29. The shift registers are then returned to the normal mode, and one or more additional vectors are applied to the input port. The shift registers are switched to the diagnostic mode, and the serial scan vectors 32 are again clocked out of the registers by way of the serial scan port. Many input vectors are applied to the input port in this manner, and the input vectors and serial scan vectors form a data base that is used to test the prototype IC. The sequence of input vectors is stored in a force memory, that is so called because it is the input vector that forces a response by the IC, and the serial scan vectors are stored in a compare memory, so called because it contains the vectors that were generated by the simulator and with which the actual vectors generated by the IC are compared. In carrying out a test on a prototype IC, the test system applies the sequence of input vectors from the force memory to the IC and compares the serial scan vectors provided by the IC with the contents of the compare memory in order to identify defects. It is usual to perform several tests on an IC, under successively more demanding conditions of, e.g. temperature, voltage levels and clock speed, in order to confirm that the IC functions not only under ideal conditions but also at the limits of its rated specifications. The different tests may be carried out using the same data base, or a special data base might be developed for a particular test. The test under ideal conditions would reveal manufacturing defects and the tests under more severe conditions would be expected to reveal design defects.
It will be recognized that each group 34 of serial scan vectors that is clocked out of the IC when the IC is placed in its diagnostic mode comprises a matrix of digits, the columns being the serial scan vectors and the rows being the sets of digits that are made available at the serial scan port of the IC on successive clocks. It will also be appreciated that since the segments of the registers might not be all of the same length, some of the digits in the matrix might be meaningless. However, there is a fixed relationship between the digit positions of the successive groups of serial scan vectors, in that the status of any particular cell of a shift register (or segment thereof) is always represented in successive groups of serial scan vectors by the same digit of the same vector.
It will be seen that the ability to examine the serial scan vectors provided by the IC permits a higher level of discrimination in testing the IC, in that it provides information regarding the likely location of a design defect.
It is, of course, important that spurious indications of defects should not be given. Therefore the data base contains, in addition to the force memory and the compare memory, a third memory that is known as a mask memory. The mask memory identifies digits of the serial scan vectors as to which no determination of correctness should be made. This might be, for example, because the value of the digit is indeterminate (it could be either a one or a zero), or its value is irrelevant to that particular portion of the test. The information contained in the mask memory is therefore used to prevent the test system from giving an error or defect indication as a result of the comparison made between particular digits of the serial scan vectors provided by the prototype IC and the corresponding digits of the compare memory.
Applying test vectors to the entire 100 or so pins of the input port may not be a very efficient way of identifying defects in an integrated circuit. By appropriate choice of the test vectors, it is possible to carry out comprehensive tests using test vectors having many fewer digits. Accordingly, some circuits are designed not only to have a normal and a diagnostic mode, but also to have a diagnostic input port having as few as 16 pins. In fact, several of these pins might be pins of the normal input port but having two internal connections (normal and diagnostic) depending on the voltage applied to a status pin.
When carrying out a serial scan test, the group of serial scan vectors is examined and the digits in that group that indicate the presence of a defect in the circuit are identified. Hitherto, this identification has simply been in the form of an indication of the position, in the sequence of groups of serial scan vectors that is generated during the test, of the digit that indicates the presence of a defect, i.e., the address of the location in the compare memory for which the value of the corresponding digit of a serial scan vector indicated a defect. The sequence of serial scan vectors may comprise as many as 64K digits, and consequently it is difficult for a user to identify meaningful patterns in the error indications.